Summary ->

Mesh Fabric (mesh_fabric_noc.sv):

• Instantiates 4 routers and 4 network interfaces in a 2×2 grid
• Uses nested genvar loops to procedurally wire cardinal ports
• Boundary tie-offs prevent packets from escaping (tx_ready=1, rx_valid=0 at edges)
• No packet loss or deadlock due to deadlock-free XY routing + packet locking

UART Subsystem (uart_noc_top.sv):

• Ingress: PC → UART RX → Command Parser → Node 0 TX Controller → Mesh
• Egress: Mesh → Echo Nodes → Node 0 RX Arbiter → Response Formatter → UART TX → PC
• Command Format: 0xA[dest_node] + 3 payload bytes
• Response Format: 0xB[src_node] + 3 payload bytes + 2 latency bytes

FPGA Results:

• Clock Frequency: 100 MHz (10 ns per cycle)
• LUT Utilization: 1,731 / 63,400 = 2.73% (leaves 97.27% for AI compute cores)
• Peak Throughput: 3.4 Gbps per directional port, 40.8 Gbps total fabric bandwidth
• Latency: Base 1-hop = 3 cycles (30 ns), multi-hop = 3 + 2×(hops-1) cycles
• Power: 0.127 W (minimal due to combinational crossbar and XY routing)
• Verified: End-to-end UART → Mesh → Echo → UART tested on hardware

Mesh Fabric - Procedural Wiring of the 2×2 Grid