Summary ->

Router_5Port is the complete switching element that ties together:

• Input buffering (FIFOs)
• Route computation (XY routers)
• Conflict resolution (arbitration + packet locking)
• Data multiplexing (crossbar)
• Output flow control (backpressure)

Network Interface bridges the core and router:

• TX: Converts 60-bit core data into 3-flit packets with timestamp injection
• RX: Reassembles 3-flit packets back to 60-bit data and calculates end-to-end latency

Together, they form the complete node of the NoC. Multiple router_5port instances are instantiated in the mesh fabric with their local ports connected to network interfaces, and their cardinal ports connected to neighboring routers. The timestamp mechanism enables cycle-accurate latency measurement, critical for understanding network performance and detecting congestion hotspots.

Router_5Port - 5-Port Switch

module router_5port #(
    parameter DATA_WIDTH  = 34,
    parameter COORD_WIDTH = 1,
    parameter FIFO_DEPTH  = 8
)(
    input  logic clk, rst_n,

    input  logic [COORD_WIDTH-1:0] router_x, router_y,      // This router's position

    input  logic [4:0] [DATA_WIDTH-1:0] rx_flit_arr,        // 5 input ports
    input  logic [4:0]                  rx_valid_arr,
    output logic [4:0]                  rx_ready_arr,

    output logic [4:0] [DATA_WIDTH-1:0] tx_flit_arr,        // 5 output ports
    output logic [4:0]                  tx_valid_arr,
    input  logic [4:0]                  tx_ready_arr
);

Port Index Convention:

• Port 0 = Local (to/from attached core)
• Port 1 = North (upward in mesh)
• Port 2 = South (downward)
• Port 3 = East (rightward)
• Port 4 = West (leftward)